( ( nil
  version "2.1"
  mapType "incremental"
  blockName "8BitAdder_TB"
  repList "spectre cmos_sch cmos.sch schematic veriloga"
  stopList "spectre"
  globalList "gnd!"
  hierDelim "."
  netlistDir "/net/plato.ee.Virginia.EDU/users2/arw5vy/simulation/8BitAdder_TB/spectre/schematic/netlist"
 )
( instViewTable
 )
( net
 )
( inst
 )
( model
( "Project/AdderBuffer/schematic" "AdderBuffer" )
( "Project/NAND/schematic" "NAND" )
( "Project/8BitRippleCarryAdder/schematic" "Project_8BitRippleCarryAdder_schematic" )
( "Project/DelVGate/schematic" "DelVGate" )
( "Project/NOR/schematic" "NOR" )
( "Project/SupplyBiasXor/schematic" "SupplyBiasXor" )
( "gnd!" "0" )
( "Project/SupplyBiasFullAdder/schematic" "SupplyBiasFullAdder" )
( "Project/8BitAdder_TB/schematic" "Project_8BitAdder_TB_schematic" )
 )
( term
 )
( param
 )
( "SupplyBiasXor" "ihnl/cds3/map" )
( "AdderBuffer" "ihnl/cds6/map" )
( "Project_8BitRippleCarryAdder_schematic" "ihnl/cds5/map" )
( "DelVGate" "ihnl/cds1/map" )
( "NAND" "ihnl/cds0/map" )
( "SupplyBiasFullAdder" "ihnl/cds4/map" )
( "Project_8BitAdder_TB_schematic" "ihnl/cds7/map" )
( "NOR" "ihnl/cds2/map" )
 )
